学术论文

      基于时钟的数字电路可重构BIST设计研究

      BIST Design Reconfigurable Digital Circuit Based on Test-per-clock

      摘要:
      研究了基于时钟的数字电路可重构内建自测试(BIST)设计.BIST不通过ATE设备加载测试矢量和检测测试响应,通过内置激励电路和响应分析电路来实现.在很大程度上降低了对ATE带宽的要求.当前电路集成度高,整体测试时可观察性和可控制性不理想,测试效果不佳,因此将大规模数字电路进行划分测试,通过基于时钟的可重构BIST设计,减少电路的测试矢量数,进而减小测试功耗.通过对可重构BIST各模块进行仿真和故障模拟验证,验证了设计的可行性.
      Abstract:
      Reconfigurable digital circuit based on test-per-clock was studied .BIST did not load test vectors and test equip-ment test response by ATE , through built-in excitation circui try and response analysis circuit .The bandwidth requirements of ATE was reduced largely .The current circuit was highly integrated , while the overall test observability and controllability were not satisfactory , and test results were not good , so the large-scale digital circuit test was divided by the number of clock reconfig-urable BIST design to reduce circuit test vectors , thereby reducing test power .By reconfigurable modules BIST simulation and fault simulation and verification , the feasibility of the design was verified .
      作者: 夏继军
      Author: XIA Ji-jun
      作者单位: 武汉大学遥感信息工程学院,湖北武汉 430079;黄冈职业技术学院机电学院,湖北黄冈 438002
      刊 名: 仪表技术与传感器 ISTICPKU
      年,卷(期): 2017, (1)
      分类号: TP334.3
      在线出版日期: 2017年3月31日