Verification of instruction set specification for an ASIP

doi：

Abstract：

In order to gain the great performance of ASIP, this paper discusses different aspects of an ASIP in-struction set specification like syntax, encoding, constraints as weld as behaviors, and introduces our ADL mod-el based methodology to check them. The automatic generation of test cases based on our straight-forward in-structian representation is shown, and the efficient generation of them with good coverage is shown as well. The verification of the constraint checker, a very important tool for programmer, is performed. Results show that the toolkit can find some errors in previous delivery tools, and the introduced methodology verifies the feasibility of our instruction set specification.

作者：
Author：	JI Jin-song[1]  MAIER Ste-fan[2]  NIE Xiao-ning[2]  ZHOU Xue-hai[1]
作者單位：	Dept. of Computer Science, USTC, Hefei 230027, China Infineon Technologies AG, Munich, Germany, 85579
期 刊：	哈爾濱工業大學學報（英文版）   EI
Journal：	JOURNAL OF HARBIN INSTITUTE OF TECHNOLOGY
年，卷(期)：	2008, 15(4)
分類號：	TP302
Keywords：	verification    ASIP    instruction set specification    ADL
機標分類號：	TV2 TU5
機標關鍵詞：	ASIP    set    automatic generation    performance    instruction    based    different    coverage    Results    aspects    syntax    errors    paper    order    test    ADL
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